Page 36 - R2017-REC-ECE-UG Syllabus

Department of ECE, REC

UNIT V IC MOSFET AMPLIFIERS 9
IC Amplifiers- IC biasing current steering circuit using MOSFET, MOSFET current sources, PMOS and
NMOS current sources. Amplifier with active loads - enhancement load, depletion load and PMOS and
NMOS current sources load, CMOS common source and source follower, CMOS differential amplifier,
CMRR.
TOTAL= 45 PERIODS

OUTCOMES:
Upon completion of the course, the students will be able to:
• Design of transistor circuits with bias stability
• Perform DC and AC analysis of single stage and multi-stage BJT amplifier circuits
• Perform DC and AC analysis of FET amplifiers
• Determine the bandwidth of BJT and FET amplifiers
• Design of IC MOSFET amplifiers with active load

TEXT BOOKS:
1. Donald .A. Neamen, Electronic Circuit Analysis and Design – 2nd Edition, Tata McGraw Hill, 2009.
2. David A., “Bell Electronic Devices and Circuits”, Oxford Higher Education Press, 5th Edition, 2010

REFERENCES:
1. Adel .S. Sedra, Kenneth C. Smith, “Micro Electronic Circuits”, 6th Edition, Oxford University Press, 2010.
2. BehzadRazavi, “Design of Analog CMOS Integrated Circuits”, Tata McGraw Hill, 2007.
3. Paul Gray, Hurst, Lewis, Meyer “Analysis and Design of Analog Integrated Circuits”, 4th Edition,John
Willey & Sons 2005
4. Millman.J. and Halkias C.C, “Integrated Electronics”, McGraw Hill, 2001.
5. D.Schilling and C.Belove, “Electronic Circuits”, 3rd Edition, McGraw Hill, 1989.
6. Robert L. Boylestad and Louis Nasheresky, “Electronic Devices and Circuit Theory”, 10th Edition, Pearson
Education / PHI, 2008.

EC 17302 DIGITAL ELECTRONICS L T P C
3 0 0 3
OBJECTIVES:
• To educate basic postulates of Boolean algebra and infer the methods for simplifying Boolean
expressions
• To illustrate the formal procedures for the analysis and design of combinational circuits and
Sequential circuits
• To extrapolate the concept in the design of synchronous and asynchronous sequential circuits
• To illustrate the concept of memories and Programmable Logic Devices
To acquire knowledge to write codes using Verilog HDL

UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES 9
Fundamentals: Boolean postulates and laws, De-Morgan’s Theorem, Principle of Duality, Boolean expression,
Minterm, Maxterm, Sum of Products (SOP), Product of Sums (POS). Minimization Techniques: Minimization
of Boolean expressions using Boolean laws, Karnaugh map, Quine McCluskey method of minimization,
Don’t care conditions.

Curriculum and Syllabus | B.E. Electronics and Communication Engineering | R2017 Page 36