Page 37 - R2017-REC-ECE-UG Syllabus
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Department of ECE, REC



                Logic  Gates:  Implementations  of  Logic  Functions  using  gates,  NAND–NOR  implementations,  TTL  and
                CMOS Logic and their characteristics, Tristate gates.


                UNIT II COMBINATIONAL CIRCUITS                                                    9
                Half adder, Full Adder, Half subtractor, Full subtractor, Code converters, Parity checker, Parity generators,
                Magnitude  Comparator,  Parallel  Binary  Adder,  Fast  Adder,  Carry  Look  Ahead  adder,  Parallel  Binary
                Subtractor,  Parallel  Binary  Adder/Subtractor,  BCD  adder,  Binary  Multiplier,  Binary  Divider,  Multiplexer,
                Demultiplexer, Decoder, Encoder.

                UNIT III SYNCHRONOUS SEQUENTIAL CIRCUITS                                           9
                Memory element: Latches, Flip-flops: RS, JK, D, T. Master-Slave, Triggering of Flip Flops, Realization of
                one  flip  flop  using  other  flip  flops.  Design  of  Synchronous  counters,  Synchronous  Up/Down  counters,
                Programmable counters, Modulo–N counter, Asynchronous Ripple or serial counter, Asynchronous Up/Down
                counter. Universal Shift Registers, Shift Register Counters: Ring counter, Shift counters. Sequence generators,
                Sequence Detector, Serial Adder/Subtractor.

                UNIT IV   ASYNCHRONOUS SEQUENTIAL CIRCUITS                                                       9
                Asynchronous  Sequential  Circuits:  Fundamental  Mode  and  Pulse  Mode  Circuits  Design,  Incompletely
                Specified State Machines, Problems in Asynchronous Circuits, Design of Hazard Free Switching circuits.
                UNIT V PROGRAMMABLE LOGIC DEVICES & HDL                                                   9
                Programmable Logic Devices(PLD): Programmable Logic Array (PLA), Programmable Array Logic (PAL),
                Field  Programmable  Gate  Arrays  (FPGA),  Implementation  of  Combinational  Logic  Circuits  using  ROM,
                PLA, PAL. Introduction to Verilog HDL with simple programs.

                                                                                      TOTAL= 45 PERIODS

                OUTCOMES:
                Students will be able to:
                    •  Reproduce the basic  postulates  of  Boolean algebra  and  recognize  &  solve  the  suitable method  for
                       simplifying Boolean expressions
                    •  Apply the procedure to Design and Implement Combinational and Sequential circuits
                    •  Design and Implement Synchronous and Asynchronous Sequential circuits.
                    •  Design of Programmable Logic Devices
                    •  Familiar with Verilog HDL codes for Combinational and Sequential circuits

                TEXT BOOKS:
                1.M. Morris Mano, “Digital Design”, 4th Edition, Prentice Hall of India Pvt. Ltd., 2008 / Pearson Education
                (Singapore) Pvt. Ltd., New Delhi, 2003.
                2. Charles H.Roth. “Fundamentals of Logic Design”, 7th Edition, Thomson Learning, 2014.

                REFERENCES:
                1.Thomas L. Floyd, “Digital Fundamentals”, 10th Edition, Pearson Education Inc, 2011.
                2. John F.Wakerly, “Digital Design”, Fourth Edition, Pearson/PHI, 2008
                3. John.M Yarbrough, “Digital Logic Applications and Design”, Thomson Learning, 2006.
                4. Donald P.Leach and Albert Paul Malvino, “Digital Principles and Applications”, 6th Edition, TMH, 2006.
                5. Donald D.Givone, “Digital Principles and Design”, TMH, 2003.



                Curriculum and Syllabus | B.E. Electronics and Communication Engineering | R2017      Page 37
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