Page 61 - R2017-REC-ECE-UG Syllabus

Department of ECE, REC

• The main focus in this course is on the transistor circuit level design and realization for digital
operation and the issues involved as well as the topics covered are quite distinct from those
encountered in courses on CMOS Analog IC design.
• Familiar about the device fabrication based on implementation strategies.
• To understand various design methodologies such as custom, semi-custom, standard cell, arrayed
logic, sea-of-gates.

UNIT I MOS TRANSISTOR PRINCIPLE 9
NMOS and PMOS transistors, Process parameters for MOS and CMOS, Electrical properties of CMOS
circuits and device modeling, Scaling principles and fundamental limits, CMOS inverter scaling, propagation
delays, Stick diagram, Layout diagrams.

UNITII COMBINATIONAL LOGIC CIRCUITS 9
Examples of Combinational Logic Design, Elmore’s constant, Logical effort, Pass transistor Logic,
Transmission gates, static and dynamic CMOS design, Power dissipation – Static & Dynamic

UNIT III SEQUENTIAL LOGIC CIRCUITS 9
Static and Dynamic Latches and Registers, Timing issues, Pipelines, Clock strategies, Memory architecture
and Memory control circuits.

UNIT IV DESIGNING ARITHMETIC BUILDING BLOCKS& TESTING 9
Data path circuits, Architectures for ripple carry adders, carry look ahead adders, High speed adders,
accumulators, multipliers, dividers, Barrel shifters, Need for testing- design for testability.

UNIT V IMPLEMENTATION AND FABRICATION OF DEVICES 9
Full custom and Semi-custom design, Standard cell design and cell libraries, FPGA building block
architectures, FPGA interconnect routing procedures, Fabrication of devices – Isolation- Mesa, Oxide, PN-
Junction isolations, self-alignment, Metallisation & Packaging.

TOTAL=45 PERIODS
OUTCOMES:
Upon completion of the course, students should be able to
• Understand concepts of MOS based circuits to realize digital logic blocks.
• Design static and dynamic MOS circuits for combinational logic functions.
• Design and construct Sequential logic Circuits using MOS gates and analyze Timing constraints.
• Design arithmetic building blocks and memory subsystems and analyze timing performance.
• Apply and implement FPGA design flow and testing logic systems.

TEXT BOOKS:
1.Neil H.E. Weste, David Money Harris ―CMOS VLSI Design: A Circuits and Systems Perspectiveǁ, 4th
Edition, Pearson , 2017 (UNIT I,II,V).
2.Jan M. Rabaey ,Anantha Chandrakasan, Borivoje. Nikolic, ǁDigital Integrated Circuits:A Design
perspectiveǁ, Second Edition , Pearson , 2016.(UNIT III,IV).

REFERENCES:
1.Sung-Mo kang, Yusuf leblebici, Chulwoo Kim ―CMOS Digital Integrated Circuits:Analysis & Designǁ,4th
edition McGraw Hill Education,2013.

Curriculum and Syllabus | B.E. Electronics and Communication Engineering | R2017 Page 61