Page 89 - R2017-REC-ECE-UG Syllabus

Department of ECE, REC

bonding- TAB and flip chip- Test process and automatic test equipment- test economics and product quality-
fault modeling.

UNIT II SEMICONDUCTOR PACKAGES AND ANALOG TESTING 9
Single chip packages or modules (SCM), Commonly used packages and advanced packages- Materials in
packages, Thermal mismatch in packages, Multichip modules (MCM)-types- System-in-package (SIP),
Packaging roadmaps, Hybrid circuits, Electrical Design considerations in systems packaging, Interconnection.
Memory Test, DSP Based Analog and Mixed Signal Test, Model based analog and mixed signal test, delay
test, IIDQ test.

UNIT III CAD FOR PRINTED WIRING BOARDS AND DIGITAL TESTING 9
Introduction to CAD and its Benefits-Design rules, Design for Reliability- Printed Wiring Board
Technologies, Board-level packaging aspects- Review of CAD output files for PCB fabrication- Photo
plotting and mask generation- Process flow-chart- Vias, PWB substrates, Surface preparation, Photo resist and
application methods, UV exposure and developing, Printing technologies for PWBs- PWB etching, PWB
etching, Resist stripping, Screen-printing technology-Through-hole manufacture process steps, Panel and
pattern plating methods, solder mask for PWBs, Multilayer PWBs, Logic and fault simulation, testability
measures- combinational and sequential circuit test generation.

UNIT IV SURFACE MOUNT TECHNOLOGY AND DESIGN FOR TESTABILITY 9
SMD benefits; Design issues, Introduction to soldering- Reflow and Wave Soldering methods to attach
SMDs, Solders, Wetting of solders, Flux and its properties, Defects in wave soldering, Vapour phase
soldering, BGA soldering and Desoldering /Repair, SMT failures, SMT failure library and Tin Whisker, Tin-
lead and lead-free solders, Thermal profiles for reflow soldering, Lead freevAlloys, Lead-free solder
considerations, Thermal Design considerations in systems packaging. Analog test bus, Fault Dictionary,
Diagnostic Tree, Testable System Design, Core Based Design and Test Wrapper Design, Test design for
SOCs.

UNIT V EMBEDDED PASSIVES TECHNOLOGY AND LOADED BOARD TESTING 9
Introduction to embedded passives, Need for embedded passives, Design Library, Embedded resistor
processes, Embedded capacitors, Processes for embedding capacitors, Case study examples. Unpowered short
circuit tests, unpowered analog tests, Powered in-circuit analog, digital and mixed signal tests, optical and X-
ray inspection procedures, functional block level design of in-circuit test equipment.
TOTAL = 45 PERIODS

OUTCOMES:
Upon completion of the course, students will be able to
• Explain different testing equipment’s.
• Design the different testing schemes for a circuit.
• Discuss the need for test process.
• Given an electronic system PCB or integrated circuit design specifications, the student should be able
to recommend the appropriate packaging style to be used, and propose a design procedure and
solution for the same.
• Design Embedded passive circuits.

TEXT BOOKS:
1.Rao R. Tummala, “Fundamentals of Microsystems Packaging”, McGraw Hill, NY, 2001
2.Michael L. Bushnell and Vishwani D. Agarwal, “Essentials of Electronic Testing for Digital, Memory &
Mixed-Signal VLSI Circuits”, Springer, 2006.

REFERENCES:
1. William D. Brown, “Advanced Electronic Packaging”, IEEE Press, 1999.
2. DimitrisGizopouilos , “Advances in Electronic Testing” , Springer 2006.

Curriculum and Syllabus | B.E. Electronics and Communication Engineering | R2017 Page 89