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D C B A Rev Rev Rev -2 -2 -2 103 103 103
Wistron Corporation Wistron Corporation Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, of of of 7 7 7
1 Taipei Hsien 221, Taiwan, R.O.C. Taipei Hsien 221, Taiwan, R.O.C. Taipei Hsien 221, Taiwan, R.O.C. CPU (RESERVED) CPU (RESERVED) CPU (RESERVED) Husk/Petra Husk/Petra Husk/Petra Sheet Sheet Sheet 1
Document Number Document Number Document Number Thursday, April 19, 2012 Thursday, April 19, 2012 Thursday, April 19, 2012
IVB IVB IVB Title Title Title Size Size Size A3 A3 A3 Date: Date: Date:
2 2
N59 N58 N42 L42 L45 L47 M13 M14 U14 W14 P13 AT49 K24 AH2 AG13 AM14 AM15 N50 A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1
5 OF 9 5 OF 9 BCLK_ITP BCLK_ITP# RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45 DC_TEST_A4 DC_TEST_C4 DC_TEST_D3 DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61 DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58 DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1
VCC_VAL_SENSE VSS_VAL_SENSE VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_DIE_SENSE IVY-BRIDGE-GP-NF IVY-BRIDGE-GP-NF 71.00IVY.A0U 71.00IVY.A0U
3 RESERVED RESERVED Dr-Bios.com 3
CPU1E CPU1E CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 RSVD47 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27
B50 C51 B54 D53 A51 C53 C55 H49 A55 H51 K49 K53 F53 G53 L51 F51 D52 L53 H43 K43 H45 K45 F48 G48 H48 K48 BA19 AV19 AT21 BB21 BB19 AY21 BA22 AY22 AU19 AU21 BD21 BD22 BD25 BD26 BG22 BE22 BG26 BE26 BF23 BE24
CFG0_TP CFG1_TP CFG2 CFG3_TP CFG4 CFG5 CFG6 CFG7
1 1 1
TP701 TP701 TP702 TP702 TP703 TP703
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
4 CFG6 Do Not Stuff Do Not Stuff 4
SSID = CPU PEG Static Lane Reversal Enabl EDP function 1:Disable 0:Enable PCIE Port Bifurcation Straps 1 2 PEG DEFER TRAINING CFG7 1 2
5 1: Normal Operation; Lane # definition matches socket pin map definition 0:Lane Reversed CFG2 1 R702 R702 1KR2J-L2-GP 1KR2J-L2-GP Muxless Muxless 2 CFG4 1 R703 R703 1KR2J-L2-GP 1KR2J-L2-GP EDP EDP 2 11: x16 - Device 1 functions 1 and 2 disabled 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled CFG5 1 R705 R70
CFG2
D CFG4 C CFG[6:5] B A
