Page 102 - Digital Electronics by harish

Input (Write) operation Output (Read) operation
S.No Sequence (Parallel Input) S.No Sequence (Serial Output)
The 4-bits parallel data are
Press the Master RESET
1. 1. taken out from ABCD
switch to clear all the FFs.
terminals.
Give the 4-bit input data to Give first clock pulse to get
2. the Parallel Input terminals 2. the second bit from SO
PI A, PI B, PI C and PI D. terminal.
Give second clock pulse to
3. Press the LOAD switch. 3. get the third bit from SO
terminal.
Give third clock pulse to
The data (4 bits) are stored
4. 4. get the fourth bit from SO
in the four FFs.
terminal.

3.3.5 Parallel IN – Parallel OUT (PIPO) Shift register

In PIPO shift register the input is given in parallel form (i.e. all the bits at the same
time) and the output is taken in parallel form. The logic diagram of PIPO shift register is
shown in figure. Four D FFs A, B, C and D are used is synchronous mode. Clock pulse is
applied to all the FFs simultaneously. The Parallel Input data PI A, PI B, PI C and PI D are given
to the PRESET terminals of the FFs through NAND gates. The NAND gates are enabled by
the LOAD switch. The Q output of FF A is given to the D input of FF B. The Q output of FF
B is given to the D input of FF C. The Q output of FF C is given to the D input of FF D. The
Parallel Output data (ABCD) are taken from the Q outputs of each FF. The CLEAR inputs of
all the FFs are connected to ground through the Master Reset switch.

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