Page 82 - Digital Electronics by harish

Figure : Logic diagram of D FF

Inputs Outputs
Condition
CLK D Q

0 0 1 Reset

1 1 0 Set

Figure : Truth table of D FF

When D = 0, J will become 0 and K will become 1, and after the clock pulse is
arrived, the output will be in RESET condition i.e. Q = 0 and = 1. When D = 1, J will
become 1 and K will become 0, and after the clock pulse is arrived, the output will be in SET
condition i.e. Q = 1 and = 0. It is clear that the FF stores the input value D.

D FF is called Data FF because this flip-flop can be used to store one bit. D FF is also
called Delay FF because the input is transferred to the output only after the arrival of the
clock pulse. . Pr and Cr inputs are used to SET and CLEAR the FF irrespective of the clock
signal.

3.1.7 Triggering of Flip-flop

The condition of the output changes from one state to another is called triggering. The
triggering is happening in FFs only due to the clock pulse. Basically there are two types of
triggering the flip-flop using clock signal:

1 Level triggering
2 Edge triggering

Figure : Clock pulse

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