Page 86 - Digital Electronics by harish

Similarly, FF C will toggle when the output of FF B toggles from 1 to 0 and FF D will
toggle when the output of FF C toggles from 1 to 0. It should be noted that FF A toggles for
every clock pulse, FF B toggles for every two clock pulses, FF C toggles for every 4 clock
pulses and FF D toggles for every eight clock pulses. The frequency of output A is ½ of the
clock frequency, output B is ¼ of clock, output C is 1/8 of clock and output D is 1/16 of
clock frequency. Hence, the four bit counter acts as a „divided by 16‟ counter.

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For the 15 clock pulse, the output is 1111. When the next (16 ) clock pulse is
applied, all the flip-flops will toggle from 1 to 0 at the same time and hence the output is
0000.The outputs of the counter during the application of each clock pulse are shown in the
truth table and also in the waveforms.

3.2.1.2 Four bit binary asynchronous (ripple) DOWN counter

The logic diagram of 4-bit binary asynchronous DOWN counter is shown in figure.
The DOWN counter counts from 1111 to 0000.

Figure :Four bit binary asynchronous (ripple) DOWN counter

Four negative edge triggered JKMS flip-flops are used in this counter. J and K inputs
of all the FFs are connected to +5v (J =1, K = 1). This makes the FFs to operate as T (Toggle)
flip-flop. The T FF changes its state (i.e. from 0 to 1 or 1 to 0) for every input clock pulse.
The clock input is applied to the first flip-flop A. The output of the FF A is given as clock
input to the second flip-flop B. The output of FF B is given as clock input to the third flip-
flop C. The output of flip-flop C is given as clock input to the fourth flip-flop D. The Q
output of all the flip-flops are taken as the counter outputs DCBA. The output A is called the
Least Significant Bit LSB) and the output D is called the Most Significant Bit (MSB). The
CLEAR (Cr) input of all the FFs are connected to ground through the Master Reset switch.

When the Master Reset switch is pressed, all the FFs are cleared and the counter
output DCBA is 0000. During the negative edge of the first clock pulse, FF A will be toggled
i.e. the Q output of A changes from 0 to 1 and output of A changes from 1 to 0. Hence,
flip-flop B also toggles. Similarly flip-flops C and D also toggle. Hence, the counter output
DCBA is 1111.

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